The microprocessor is sometimes referred to as the 'brain' of the personal computer, and is responsible for the processing of the instructions which make up computer software. It houses the central processing unit, commonly referred to as the CPU, and as such is a crucially important part of the home PC. However, how many people really understand how the chip itself works?
CPU Structure
This section, using a simplified model of a central processing unit as an example, takes you through the role of each of the major constituent parts of the CPU. It also looks more closely at each part, and examines how they are constructed and how they perform their role within the microprocessor.
This section, using a simplified model of a central processing unit as an example, takes you through the role of each of the major constituent parts of the CPU. It also looks more closely at each part, and examines how they are constructed and how they perform their role within the microprocessor.
Instruction Execution
Once you are familiar with the various elements of the processor, this section looks at how they work together to process and execute a program. It looks at how the various instructions that form the program are recognised, together with the processes and actions that are carried out during the instruction execution cycle itself.
Once you are familiar with the various elements of the processor, this section looks at how they work together to process and execute a program. It looks at how the various instructions that form the program are recognised, together with the processes and actions that are carried out during the instruction execution cycle itself.
Further Features
Now that the basics have been covered, this section explores the further advancements in the field of microprocessor architecture that haveoccured in recent years. Explanations of such techniques as pipelining and hyperthreading are provided, together with a look at cache memory and trends in CPU architecture.
Now that the basics have been covered, this section explores the further advancements in the field of microprocessor architecture that haveoccured in recent years. Explanations of such techniques as pipelining and hyperthreading are provided, together with a look at cache memory and trends in CPU architecture.
The first section of this tutorial related to the structure of the central processing unit. Please click the button marked with the next arrow below to proceed.
Following on from looking at the structure and architecture of the central processing unit itself, we shall now look at how the CPU is used to execute programs and make the computer as a whole run smoothly and efficiently. To do this, we must take a step back from concentrating solely on the processor, and look at the complete computer unit.
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A flow diagram illustrating the flow of data within the PC during program execution and the saving of data. Further explanation can be found below.
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When software is installed onto a modern day personal computer (most commonly from a CD-ROM, though other media or downloading from the internet is also common), code comprising the program and any associated files is stored on the hard drive. This code comprises of a series of instructions for performing designated tasks, and data associated with these instructions. The code remains there until the user chooses to execute the program in question, on which point sections of the code are loaded into the computers memory.
The CPU then executes the program from memory, processing each instruction in turn. Of course, in order to execute the instructions, it is necessary for the CPU to understand what the instruction is telling it to do. Therefore, recognition for instructions that could be encountered needs to be programmed into the processor. The instructions that can be recognized by a processor are referred to as an 'instruction set', and are described in greater detail on the next page of the tutorial.
Once the instruction has been recognized, and the actions that should be carried out are decided upon, the actions are then performed before the CPU proceeds on to the next instruction in memory. This process is called the 'instruction execution cycle', and is also covered later on in this tutorial. Results can then be stored back in the memory, and later saved to the hard drive and possibly backed up onto removal media or in seperatelocations. This is the same flow of information as when a program is executed only in reverse, as illustrated in the diagram above.
The system bus is a cable which carries data communication between the major components of the computer, including the microprocessor. Not all of the communication that uses the bus involves the CPU, although naturally the examples used in this tutorial will centre on such instances.
The system bus consists of three different groups of wiring, called the data bus, control bus and address bus. These all have seperateresponsibilities and characteristics, which can be outlined as follows:
Control Bus
The control bus carries the signals relating to the control and co-ordination of the various activities across the computer, which can be sent from the control unit within the CPU. Different architectures result in differing number of lines of wire within the control bus, as each line is used to perform a specific task. For instance, different, specific lines are used for each of read, write and reset requests.
The control bus carries the signals relating to the control and co-ordination of the various activities across the computer, which can be sent from the control unit within the CPU. Different architectures result in differing number of lines of wire within the control bus, as each line is used to perform a specific task. For instance, different, specific lines are used for each of read, write and reset requests.
Data Bus
This is used for the exchange of data between the processor, memory and peripherals, and is bi-directional so that it allows data flow in both directions along the wires. Again, the number of wires used in the data bus (sometimes known as the 'width') can differ. Each wire is used for the transfer of signals corresponding to a single bit of binary data. As such, a greater width allows greater amounts of data to be transferred at the same time.
This is used for the exchange of data between the processor, memory and peripherals, and is bi-directional so that it allows data flow in both directions along the wires. Again, the number of wires used in the data bus (sometimes known as the 'width') can differ. Each wire is used for the transfer of signals corresponding to a single bit of binary data. As such, a greater width allows greater amounts of data to be transferred at the same time.
Address Bus
The address bus contains the connections between the microprocessor and memory that carry the signals relating to the addresses which the CPU is processing at that time, such as the locations that the CPU is reading from or writing to. The width of the address bus corresponds to the maximum addressing capacity of the bus, or the largest address within memory that the bus can work with. The addresses are transferred in binary format, with each line of the address bus carrying a single binary digit. Therefore the maximum address capacity is equal to two to the power of the number of lines present (2^lines).
The address bus contains the connections between the microprocessor and memory that carry the signals relating to the addresses which the CPU is processing at that time, such as the locations that the CPU is reading from or writing to. The width of the address bus corresponds to the maximum addressing capacity of the bus, or the largest address within memory that the bus can work with. The addresses are transferred in binary format, with each line of the address bus carrying a single binary digit. Therefore the maximum address capacity is equal to two to the power of the number of lines present (2^lines).
This concludes the look at the simplified model processor that will be used for the remainder of this tutorial. The next section will look at theinstruction execution process, and how these different parts work together to execute programs. However, before that, there's a chance to test what you've learnt in this section regarding processor architecture. Click the next arrow below to take a short quiz relating to this section of the tutorial.
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The simplified model of the central processing unit, with the system bus highlighted in red. Click on a different section for more information.
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As outlined in the introduction to this section, for a processor to be able to process an instruction, it needs to be able to determine what the instruction is asking to be carried out. For this to occur, the CPU needs to know what actions it may be asked to perform, and have pre-determined methods available to carry out these actions. It is this idea which is the reasoning behind the 'instruction set'.
When a processor is executing a program, the program is in a machine language. However, programmers almost never write their programs directly into this form. While it may not have been originally written in this way, it is translated to a machine language at some point before execution so that it is understandable by the CPU. Machine language can be directly interpreted by the hardware itself, and is able to be easily encoded as a string of binary bits and sent easily via electrical signals.
The instruction set is a collection of pre-defined machine codes, which the CPU is designed to expect and be able to act upon when detected. Different processors have different instruction sets, to allow for greater features, easier coding, and to cope with changes in the actual architecture of the processor itself. Each machine code of an instruction set consists of two seperate fields:
Opcode
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Operand(s)
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The opcode is a short code which indicates what operation is expected to be performed. Each operation has a unique opcode. The operand, or operands, indicate where the data required for the operation can be found and how it can be accessed (the addressing mode, which is discussed in full later). The length of a machine code can vary - common lengths vary from one to twelve bytes in size.
The exact format of the machine codes is again CPU dependant. For the purpose of this tutorial, we will presume we are using a 24-bit CPU. This means that the minimum length of the machine codes used here should be 24 binary bits, which in this instance are split as shown in the table below:
Opcode
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6 bits (18-23)
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- Allows for 64 unique opcodes (2^6)
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Operand(s)
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18 bits (0-17)
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- 16 bits (0-15) for address values
- 2 bits (16/17) for specifying addressing mode to be used |
Opcodes are also given mnemonics (short names) so that they can be easily referred to in code listings and similar documentation. For example, an instruction to store the contents of the accumulator in a given memory address could be given the binary opcode 000001, which may then be referred to using the mnemonic STA (short for STore Accumulator). Such mnemonics will be used for the examples on upcoming pages.
Once a program is in memory it has to be executed. To do this, each instruction must be looked at, decoded and acted upon in turn until the program is completed. This is achieved by the use of what is termed the 'instruction execution cycle', which is the cycle by which each instruction in turn is processed. However, to ensure that the execution proceeds smoothly, it is is also necessary to synchronise the activites of the processor.
To keep the events synchronised, the clock located within the CPU control unit is used. This produces regular pulses on the system bus at a specific frequency, so that each pulse is an equal time following the last. This clock pulse frequency is linked to the clock speed of the processor - the higher the clock speed, the shorter the time between pulses. Actions only occur when a pulse is detected, so that commands can be kept in time with each other across the whole computer unit.
The instruction execution cycle can be clearly divided into three different parts, which will now be looked at in more detail. For more on each part of the cycle click the relevant heading, or use the next arrow as before to proceed though each stage in order.
Fetch Cycle
The fetch cycle takes the address required from memory, stores it in the instruction register, and moves the program counter on one so that it points to the next instruction.
The fetch cycle takes the address required from memory, stores it in the instruction register, and moves the program counter on one so that it points to the next instruction.
Decode Cycle
Here, the control unit checks the instruction that is now stored within the instruction register. It determines which opcode and addressing mode have been used, and as such what actions need to be carried out in order to execute the instruction in question.
Here, the control unit checks the instruction that is now stored within the instruction register. It determines which opcode and addressing mode have been used, and as such what actions need to be carried out in order to execute the instruction in question.
Execute Cycle
The actual actions which occur during the execute cycle of an instruction depend on both the instruction itself, and the addressing mode specified to be used to access the data that may be required. However, four main groups of actions do exist, which are discussed in full later on.
The actual actions which occur during the execute cycle of an instruction depend on both the instruction itself, and the addressing mode specified to be used to access the data that may be required. However, four main groups of actions do exist, which are discussed in full later on.
Clicking the next arrow below will take you to further information relating to the fetch cycle.
The first of the three addressing modes to be looked at is immediate addressing. When writing out the code in mnemonic form, operands that require this mode are marked with a # symbol. With immediate addressing, the data required for execution of the instruction is located directly within the operands of the instruction itself. No lookup of data from memory is required.
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